The integrated circuit industry continues to explore techniques to pack more circuits onto a given semiconductor substrate. Accordingly, more and more thought is being devoted to orienting the various devices in planar fashion along the surface of the substrate. Thought is also being devoted to orienting the devices vertically either by building devices "up" from the substrate surface or by burying devices in trenches formed within the face of the semiconductor body.
Currently, a majority of circuits and memory chips are fabricated using metal-oxide semiconductor field effect transistor (MOSFET) technology. This technology places conventional horizontal MOSFET circuits having a source and drain at the same level on the substrate. With appropriate voltage adjustments, the circuits can be reduced in area simply by scaling to smaller dimensions. Specifically, all dimensions of the various process masks can be uniformly reduced so that the resulting circuitry is fabricated in a smaller area on the semiconductor wafer. Unfortunately, the process of scaling down a MOSFET circuit presents certain difficulties.
Reduction of the channel length has been the single biggest variable in reducing the dimensions of field effect transistors. Conventional horizontal field effect transistors rely on the capability of photolithographic tools to define the channel length. Therefore, the performance of conventional field effect transistors is limited by the capability of the available photolithographic tools. As of 1999, the photolithographic limit on the channel length is about 0.15 microns (1,500 angstroms).
In addition to reducing the field effect transistor dimensions, reduction of the channel length offers performance advantage. In thin film field effect transistors, the device output currents and high speed are dependent on the length of the semiconductor conduction channel formed between the source electrode and the drain electrode under the influence of the gate electrode. The source-to-drain output current is inversely proportional to the channel length, while the operating frequency is inversely proportional to the square of the channel length. Thus, when the channel length of the device is reduced by an order of magnitude, for example from 2 to 0.2 microns, the output current should increase 10 fold and the operating speed or frequency increases approximately 100 fold.
The operating speed also depends on the interelectrode capacitance of the device; a large capacitance causes slower operation. The extension of the gate electrode over the source and drain electrodes is a common source of interelectrode capacitance, and is referred to as "overlap" parasitic capacitance. The overlap is a result of limited photolithographic resolution.
Large area arrays of multiple thin film field effect transistors may be prepared by standard 0.2 micron photolithography. When so prepared, the minimum channel length that can be achieved in planar thin film transistor arrays is limited by photolithographic feature and is typically on the order of 0.2 microns as of 1999. One way to overcome the limitations inherent in large area photolithographic resolution is to use a vertical structure in which channel length is determined by vertical separation of the source and drain electrodes.
There remains a need for a field effect transistor design capable of achieving short channel length and faster operation that is not constrained by photolithographic limits. Therefore, an object of the present invention is to provide a vertical channel FET having reduced dimensions as compared to conventional field effect transistors, particularly a reduced channel length between the source and drain. A related object is to provide a vertical channel FET that is not constrained by photolithographic limits. Another object is to provide a vertical channel FET having relatively fast operation. Still another object of the present invention is to overcome the shortcomings of conventional field effect transistors. Other objects and advantages will become apparent from the following detailed description.